Aubrey Jaffer jaffer@ai.mit.edu
SIMSYNCH is a digital logic simulator. The design files are comprised of Scheme definitions and expressions. These design files can be run as a Scheme program at high speed. The design files can also be translated into formats suitable for logic compilers.
SIMSYNCH simulates blocks of synchronous logic, signals whose states change simultaneously on a clock signal transition. Each block also has a reset signal, which forces all signals to the state specified in the design file. SIMSYNCH can simultaneously simulate multiple blocks with different clocks and resets.
Blocks can contain multiple devices; Devices can contain multiple blocks.
For a list of the features that have changed since the last SIMSYNCH release, see the file `ANNOUNCE'. For a list of the features that have changed over time, see the file `ChangeLog'.
The author can be reached as `jaffer@ai.mit.edu'. The most recent information about SIMSYNCH can be found on SIMSYNCH's WWW home page:
http://swissnet.ai.mit.edu/~jaffer/SIMSYNCH.html.
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