School of Computer Science

CDA 4150: Computer Architecture (Spring 2006)

Instructor: Prof. Euripides Montagne

Lecture Meetings: MW 12p.m. to 1:15 p.m. (ENG 224)

Office hours: MW from 10:30am to 11:30a.m, Tuesday from 12pm to 2pm and Thursday from 12pm to 1pm(CSB 239)

eurip@cs.ucf.edu Tel: 407-823-2684


TA: HONGLIANG GAO
Office Hours: Monday, 2:30p.m. - 4:30p.m. (CSB 107)
hgao@cs.ucf.edu Tel: 407-823-3228

Announcements

  • New! Grades of Final project with solution and grading criteria posted. May 4th.
  • New! Final Project posted. Due Apr. 24!
  • Project 1 grades posted. April 3rd. If you have any questions about your grade, please contact me before April 17th. After April 17th, all grades will be finalized.
  • Two new notes posted. Mar 29th.
  • Deadline of Project 1 is extended to Friday Mar 10th 11:59pm! For those of you still cann't make .cshrc work, please run "cp ~hgao/.cshrc ~/" to get it.
  • Remember to change your Makefile as described below in "Project Help"! Mar 6th.
  • Please use monroe.cs.ucf.edu instead of olympus as the server for your verilog project. Mar 2nd.
  • Project 1 posted. Due Mar 8th 11:59pm!
  • Welcome to the home of CDA4150 Spring 2006!

Project Help

Verilog:

  • Read this verilog manual(online / pdf) first.
  • This is Prof. Mark Heinrich's help page for CDA 4150.
  • Project Submission:
    • For those of you got "Missing README file" error, please change the access permission of your project with these commands:
      cd ~/
      chmod -R 755 cda4150
      Then submit your project
      After submission, use "chmod -R 700 cda4150" to remove readable permission of your project. Otherwise, others can read your project and copy it!

Project 1:

  • Sample .cshrc file.
  • For those of you got this error:
    Make : make
    C compiler : gcc -O2
    C++ compiler: c++ -O2
    CFLAGS : -DSUN -D_BSD_SIGNALS -I. -I/home/heinrich/Sim/lib

    make[1]: vcs: Command not found
    make[1]: *** [demofulladder] Error 127
    make: *** [all] Error 2

    Remember to use "source ~/.cshrc" first after you login. Then you should be able to make.

  • After you change those .v files, remember to update Makefile to compile corresponding part. For example, after you changed file byteadder.v and/or demobyteadder.v, change this line of your Makefile:
    from "TARGETS=demofulladder" to "TARGETS=demobyteadder".
    Then make and run simv to check your code.

    If you don't want to change Makefile, you can also use "make demobyteadder" to make it.

The Semester Plan: Tentative.

  • Week 1- Logistics, team organization. Introduction to computer architecture.
    - Flynn’s Taxonomy
    Week 2 – SISD architecture, register transfer notation.
    – Cost of a Die, Performance, Amdahl's Law
    Week 3 – ISA, instruction encodings , addressing modes. Interrupt handling( Case
    Studies: IBM 360, B5000, MIPS)
    - Computer Arithmetic, Floating point arithmetic, Pipelining in the ALU.
    Week 4 - Vector processing, Memory Interleaving(Cray-1).
    - Chaining, loop unrolling, skewed matrix representation.
    Week 5 – Review
    – First Midterm Exam.
    Week 6 – The Processor Data Path and Control Unit.
    - Pipeleined Execution. Pipeline data path.
    Week 7 - Pipeline Data Hazards.
    - Control Hazards. Exception Handling.
    Week 8 - ILP:Superscalars. Scoreboarding(CDC6600), Tomasulo's Algorithm.
    - MIPS and IA-64 Architectures.
    Week 9 – Systolic Arrays and Data Flow Architectures.
    Week 10 - Review
    - Second Midterm Exam.
    Week 11 - Cache Memory
    - Virtual Memory
    Week 12 - I/O Devices and Performance Measures.
    - RAID
    Week 13 – Detecting Parallelism in Programs.
    - Multiprocessors.
    Week 14 – Interconnection Networks
    -Review
    Final Exam April 26th, 2006

Syllabus

Handouts: