INFO. FLOW FOR COMPILED LANGUAGES Source ---> [ Compiler ] ---> Object Code Code Other | Module(s) | \ | \ v Library v(Static) Code --> [Linker] | | v Executable (ELF) | | v [Loader] Dynamic | Library - | Code | | v v (Dynamic)<-Running [Linker]-->Program [Operating System (OS)] FLOW FOR INTERPRETED LANGUAGES Source--> [ Interpreter ]--> (Bytecode) Other | Module(s) | \ | \ | Library v v Code --> [Virtual Dynamic > Machine] Library / Code [Operating System (OS)] OBJECT FILES def: an *object file* holds the compiled code for a program module; it can be linked into a complete executable. What data is needed? - code (often called the "text") - data (sometimes just reserving space) - metadata (sizes of text and data) - symbols (used and exported) OBJECT FILE FORMAT header - magic number (identifies type of file) - other metadata (machine type, date,...) - starting address of the code - uninitialized data size - symbol table size - entry points and their sizes text (code) - machine code data section - sizes and initial values of data symbol table - names of imported subroutines or data - names of exported subroutines and data VON NEUMANN ARCHITECTURE (HARDWARE) /------> [ PC ] | | | v |------> [ MAR ] | | | v | [ MEMORY ] | [ (RAM) ] | [ ] | | | v IR [OP|ADDR] <-> [ MDR ] <--> [ ACCUM ] | ^ | ^ | | | | v v v | /---------\ \-----------------/ | / DECODER \ \ ALU / | \-----------/ > \-------------/ | | / > | | v /--/ / v | [Control] / \------------/ [Unit ] -----/ WARNING! This is not a description of HW1's ISA! Different instructions! It's The "Tiny Machine", NOT for HW1 INSTRUCTION CYCLE 1. Fetch: IR <- MEMORY[PC] by: MAR <- PC MDR <- MEMORY[MDR] IR <- MDR 2. Execute: ; Advance the PC ; decode and ; execute instruction in IR PC <- PC + 1 ; next instruction EXECUTING LOD ; put IR's ADDR field into MAR MAR <- IR.ADDR ; fetch location into MDR MDR <- MEMORY[MAR] ; move MDR's contents into ACCUM ACCUM <- MDR EXECUTING STO ; put IR's ADDR field into MAR MAR <- IR.ADDR ; move ACCUM into MDR MDR <- ACCUM ; put MDR into MEMORY at address in MAR MEMORY[MAR] <- MDR EXECUTING SUB ; put IR's ADDR field into MAR MAR <- IR.ADDR ; fetch location into MDR MDR <- MEMORY[MAR] ; Compute ACCUM - MDR ACCUM <- ACCUM - MDR EXECUTING HLT ; Stop execution, program ends normally Stop executing instructions EXECUTING JMP ; put IR's ADDR field into PC PC <- IR.ADDR EXECUTING SKZ ; If ACCUM is 0 then skip next instr. if (ACCUM == 0) then PC <- PC + 1 if (COND) then S1 else S2; S3 gets translated to SKZ JMP
JMP
: JMP
:
: TRANSLATING WHILE LOOPS while (COND) { S } S2 is translated into: : SKZ JMP
JMP
: EXECUTING CIN ; read a single char from input ACCUM <- getc(stdin) EXECUTING COU ; write ACCUM to output as a character putchar(ACCUM) EXECUTING OR ; put IR's ADDR field into MAR MAR <- IR.ADDR ; fetch location into MDR MDR <- MEMORY[MAR] ; Compute ACCUM | MDR ACCUM <- ACCUM | MDR REFLECTING CONDITIONS IN HARDWARE Use a register to indicate value in ACCUM Z is 1 when ACCUM is 0 G is 1 when ACCUM is positive L is 1 when ACCUM is negative x86 architecture has a program status word containing: Interrupt flags Supervisory mode flag condition codes SUMMARY OF TINY MACHINE ISA OP CODE MNEMONIC ADDR? 1 LOD Y 2 STO Y 3 ADD Y 4 SUB Y 5 CIN ? 6 COU ? 7 HLT 8 JMP Y 9 SKZ 10 SKG 11 SKL 12 OR Y 13 AND Y 14 NOT FOR YOU TO DO Write a program in machine code to: - input two chars - print Y (89) if they are the same - print N (78) otherwise ASSEMBLY LANGUAGE FEATURES - Mnemonics for opcodes - Names for locations - Initialization of data - Comments EXAMPLE IN ASSEMBLY LANGUAGE .begin ; text (code) section ; read a char into c1 start: CIN STO c1 CIN ; read char into ACCUM SUB c1 SKZ JMP n ; jump to n if different LOD yc ; output "Y\n" COU LOD nl COU HLT n: LOD nc ; output "N\n" COU LOD nl COU HLT .end start ; data section .data c1 1 0 .data yc 1 89 .data nc 1 78 .data nl 1 10 ASSEMBLY LANGUAGE DIRECTIVES Help structure the program: DEBUGGER TRACE Addr OP ADDR 0 LIT 89 1 STO 89 2 LIT 78 3 STO 78 4 LIT 10 5 STO 100 6 CIN 0 7 STO 103 8 CIN 0 9 SUB 103 10 SKZ 0 11 JMP 17 12 LOD 89 13 COU 0 14 LOD 100 15 COU 0 16 HLT 0 17 LOD 78 18 COU 0 19 LOD 100 20 COU 0 21 HLT 0 Tracing ... PC: 0 ACCUM: 0 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 100: 0 ... ==> addr: 0 LIT 89 PC: 1 ACCUM: 89 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 100: 0 ... ==> addr: 1 STO 89 PC: 2 ACCUM: 89 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 89: 0x59 90: 0x0 ... 100: 0 ... ==> addr: 2 LIT 78 PC: 3 ACCUM: 78 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 89: 0x59 90: 0x0 ... 100: 0 ... ==> addr: 3 STO 78 PC: 4 ACCUM: 78 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 0 ... ==> addr: 4 LIT 10 PC: 5 ACCUM: 10 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 0 ... ==> addr: 5 STO 100 PC: 6 ACCUM: 10 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... ==> addr: 6 CIN 0 PC: 7 ACCUM: 97 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... ==> addr: 7 STO 103 PC: 8 ACCUM: 97 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 8 CIN 0 PC: 9 ACCUM: 97 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 9 SUB 103 PC: 10 ACCUM: 0 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 10 SKZ 0 PC: 12 ACCUM: 0 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 12 LOD 89 PC: 13 ACCUM: 89 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 13 COU 0 YPC: 14 ACCUM: 89 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 14 LOD 100 PC: 15 ACCUM: 10 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 15 COU 0 PC: 16 ACCUM: 10 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... ==> addr: 16 HLT 0 PC: 17 ACCUM: 10 memory: 0: 0x59 1: 0x2000059 2: 0x4e 3: 0x200004e 4: 0xa 5: 0x2000064 6: 0x5000000 7: 0x2000067 8: 0x5000000 9: 0x4000067 10: 0x9000000 11: 0x8000011 12: 0x1000059 13: 0x6000000 14: 0x1000064 15: 0x6000000 16: 0x7000000 17: 0x100004e 18: 0x6000000 19: 0x1000064 20: 0x6000000 21: 0x7000000 22: 0x0 ... 78: 0x4e 79: 0x0 ... 89: 0x59 90: 0x0 ... 100: 10 101: 0 ... 103: 97 104: 0 ... BACKGROUND: SPEED OF COMPUTER MEMORY Speed Cost/bit ======= ========= Fastest Expensive Registers Cache Memory (SRAM) RAM (Main Memory, DRAM) Spinning Magnetic Disk (HDD) External Drives (Tape, Optical) Slowest Cheapest REGISTER MACHINE ARCHITECTURE - Word-oriented (4 bytes) but byte-addressed - All instructions 32 bits long must be aligned on word boundary - 32 registers REGISTER MACHINE ISA Arithmetic and logic instructions - work with 3 registers - format: [op:6|rs:5|rt:5|rd:5|shift:5|func:6] - example: ADD s t d means GPR[d] <- GPR[s] + GPR[d] Intermediate operand instructions - work with 2 registers - format: [ op:6 | rs:5 | rt:5 | immed: 16 ] - example: ADDI s t i means GPR[t] <- GPR[s] + sgnExt(i) where sgnExt(i) i sign extended Jump instructions - work with a 26 bit address - format: [ op:6 | addr: 26 ] - example: JMP a means PC <- formAddress(a) System call instructions - work with a code and function - format: [ op:6 | code:20 | func:6 ] - example SYS 10 means stop the program's execution where sgnExt(0xFFFF) = 0xFFFFFFFF sgnExt(0x0000) = 0x00000000 sgnExt(0x0001) = 0x00000001 formAddress concatenates high bits of PC with the 26 bit address + 2 bits of 0 (to align on a word) so if PC = 0xFACADE, then formAddress(0x00DECADE) = 0x007B2B78