Signals and Pins

These functions are the "pure" interface to defining signals and pins. They were created after the macro interface of the next section. I don't yet use these functions directly; if you do, please send suggestions for improvements.

Function: synch:insert-check expr

Adds the scheme expression expr to the body of the *block* simulator. Check expressions are evaluated once per clock cycle of their block while the block's reset is deasserted.

Check expressions are evaluated in the order in which they are defined by synch:insert-check.

Function: synch:define-pin ptag signal pin-type pin-name output-enable paired-input

Associates all of the physical attributes of the symbol signal. Describing the signal flow of signal, pin-type is one of

• output
• input/output
• wire-and
• wire-or
• clock
• input
• unused
• internal

Function: synch:define-signal signal defining-ptag signal-type reset-state next-function

Associates the initial state and transitions for signal.

reset-state is the value held by this signal while reset-name for this block is asserted. reset-state should be a boolean for single signals and an integer for vectorized signals.

The scheme expression next-function determines the values for signal when the block reset is deasserted.

signal-type is one of

registered

signal will take the value next-function at the next rising edge of this block's clock signal.

registered-input

signal will take the value next-function at the next rising edge of this block's clock signal. But when compiling into the hardware description language, signal's input is the pin named signal.

combinatorial

signal follows the value next-function before the next rising edge of this block's clock signal. combinatorial is not yet implemented.

hidden

macro

signal follows the value next-function before the next rising edge of this block's clock signal. hidden is used to specify the input side of input/output pins.

Function: synch:define-bus name float-limit clause1 clause2 ...

Each clause is a (quoted) list of two expressions, an output-enable signal and a data value. That data value becomes the value of the bus if its output-enable signal is non-false.

If the last clause is (#t value), then value is returned whenever no other clause is active.

synch:define-bus instantiates checks whether name is being driven from multiple sources to different values. It also creates a check whether name is undriven for float-limit cycles. If the feature check-turnaround is provided when `simsynch.scm' is loaded, synch:define-bus will also check the at least one cycle separates driving of name from different sources.

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