Macros for Signals and Pins

This is the original form of simsynch. It grew over time, so it is poorly organized. But I have a lot of modules written this way.

Macro: synch:defcheck expr

Adds the scheme expression expr to the body of the *block* simulator. Check expressions are evaluated once per clock cycle of their block while the block's reset is deasserted.

Check expressions are evaluated in the order in which they are defined by synch:defcheck.

Macro: synch:pre signal

Synch:pre is a macro that saves typing. synch:pre retrieves the next-function expression of signal. Using synch:pre has the same effect of inserting the second argument of the synch:set! specifying signal.

The following defmacros treat their pin-name, signal, name argument specially. If the symbol contains a colon (`:'), the part before the colon is the ptag and the part after is the signal name. If the colon is the last character, then the name is #f, which is used for signals which do not connect to pins. If the part after the colon is a number, then the (pin's) name is that number.

synch:set!, synch:set/reset!, and synch:pre do not accept `:' encoded signal-names.

If the pin-name argument is ? (question-mark), this indicates that the fitter should assign a pin(s) for this signal. The assignments for bussed signals can be a range of pin names (eg. `addr[12..0]') or a parenthesized list of pin names or numbers (eg. `(34 25 61 12').

Macro: synch:defmacro name expression

Defines name to be a signal of type macro whose value is expression. name will translate to a macro in the hardware description language which replaces name with expression.

Macro: synch:defshare ptag:pin-name name

Macro: synch:defshare pin-name ptag:name

Identifies pin-name of chip ptag with an already defined signal name. synch:defshare is used when connecting inputs in one package to outputs on another. These outputs need originate from chips which are generated; they may also come from hidden models.

Macro: synch:definput pin-name name expression

Defines a pin used only for input. expression is computed as a hidden macro.

Macro: synch:defreginput pin-name name expression

Defines a pin used only for input, but whose signal is delayed by one clock cycle.

Macro: synch:define pin-name signal reset-state pin output-enable

Macro: synch:define pin-name signal reset-state pin output-enable next-function

Defines a synchronous signal and pin. synch:define defines all of the information synch:define-pin and synch:define-signal do. If next-function is absent, then it must be supplied by use of synch:set!.

output-enable is a boolean valued expression which controls whether the signal drives the pin(s). pin is #f or a symbol which names the signal at the pin. Note that the values of pin will necessarily match the values of signal only while output-enable is #t. signal and pin can be the same symbol if you have no need to access the (possibly undriven) signal.

(synch:define #f XP:tl-raw #t #f #f)

defines an internal signal with initial value #t.

(synch:define 36 XP:dloe- #t dloe- #t)

defines an output named dloe-.

(synch:define (34 33 32) XP:stpsz-out[2..0] #.tpsz-tag stpsz[2..0] dloe-)
(synch:defmacro HID:stpsz[2..0]
                (cond (dloe- stpsz-out[2..0])
                      ((not last-dloe-) dly:-fo-tag-reg)
                      (else -1)))

defines bussed pins stpsz[2..0] sometimes driven by the vectorized signal stpsz-out[2..0], which is always available to the design. HID:stpsz[2..0] emulates the signals at the pins which can be driven from various sources.

reset-state is the value held by this signal while reset-name for this block is asserted. reset-state should be a boolean for single signals and an integer for vectorized signals.

Macro: synch:set! signal next-function

The scheme expression next-function determines the values for signal while the block's reset is deasserted.

Macro: synch:set/reset! signal turn-on turn-off

is a variant of synch:set! which simulates a clocked set/reset flip-flop. The turn-off expression overrides turn-on when both are simultaneously true; in which case a warning is also generated.

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