SIMSYNCH can translate its register-transfer-level designs to
MACHXL or Verilog formats. The bulk of the work is
performed by the files `scm2mach' and `scm2vrlg'. The file
`run.scm' defines translate
, which drives the conversion.
The symbol design should correspond to a file named `design.scm', which contains the definitions.
The symbol target-language can be:
machxl
translate
creates a file nameed `design.pds' with the
MACHXL definitions.
verilog
SIMSYNCH translates the following syntaxes. Remember that you are limited to this set only for signals which will be translated for the benefit of a logic compiler.
and
and
.
or
number-or
number-or
for combining clauses which return only vectorized
values or #f
.
if
(if <test> <consequent> <alternate>)
.
case
casev
casev
is an extension of standard Scheme case
: Each
clause of a case
statement must begin with a list of literal
datums, the corresponding list in a casev
statement may
contain either literal datums or the names of symbolic constants
preceded by a comma. A casev
statement is equivalent to a
case
statement in which all symbolic constants preceded by commas
have been replaced by the values of the constants. This use of comma,
(or, equivalently, unquote
) is similar to that of
quasiquote
except that the unquoted expressions must be
symbolic constants.
Symbolic constants are defined using defconst
, their values are
substituted in the head of each casev
clause during macro
expansion. In practice defconst
constants should be defined
before use.
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